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generalplus technology inc. reserves the right to change this documentation without prior notice. information provided by gene ralplus technology inc. is believed to be accurate and reliable. however, generalplus technology inc. makes no warranty for any errors which may appear in this document. contact generalplus technology inc. to obtain the latest version of device specifications before plac ing your order. no responsibility is assumed by generalplus technology inc. for any infringement of patent or other rights of third parties which may result from its use. in addition, generalplus products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the expre ss written approval of generalplus. oct 01, 2013 version 1.7 g g p p c c e e 0 0 0 0 1 1 a a 1 1 6 6 - - b b i i t t s s o o u u n n d d c c o o n n t t r r o o l l l l e e r r w w i i t t h h 2 2 5 5 6 6 k k x x 1 1 6 6 f f l l a a s s h h m m e e m m o o r r y y
gpce001a ? generalplus technology inc. proprietary & confidential 2 oct 01, 2013 version: 1.7 table of contents page 1. general description .................................................................................................................... ...................................................... 3 2. application field.......................................................................................................................... ........................................................ 3 3. features....................................................................................................................... ........................................................................... 3 4. block diagram ........................................................................................................................ .............................................................. 4 5. signal descriptions................................................................................................................... ......................................................... 5 5.1. pad a ssignment ............................................................................................................................... .................................................. 7 5.2. pin m ap ............................................................................................................................... ................................................................ 8 6. functional description .................................................................................................................... ................................................ 9 6.1. cpu ............................................................................................................................ ......................................................................... 9 6.2. m emory ............................................................................................................................... ................................................................ 9 6.3. pll, c lock , p ower saving m ode ............................................................................................................................... ...................... 10 6.4. p ower s aving m ode ............................................................................................................................... .......................................... 10 6.5. cpu h alt m ode ............................................................................................................................... .................................................. 10 6.6. l ow v oltage d etection and l ow v oltage r eset ........................................................................................................................... 10 6.7. i nterrupt ............................................................................................................................... ............................................................11 6.8. i/o ............................................................................................................................ ...........................................................................11 6.9. t imer /c ounter ............................................................................................................................... .................................................. 13 6.10. s leep mode , w akeup , h alt mode , and w atchdog ........................................................................................................................... 14 6.11. adc (a nalog to d igital c onverter ) / dac ............................................................................................................................ ........ 14 6.12. 16 bits dac a udio d river ............................................................................................................................... ................................. 14 6.13. s erial i nterface i/o (sio).......................................................................................................................... ...................................... 14 6.14. spi ............................................................................................................................ ......................................................................... 15 6.15. a udio a lgorithm ............................................................................................................................... ................................................ 15 6.16. s ecurity f unction ............................................................................................................................... ............................................ 15 7. electrical specifications ................................................................................................................. ............................................ 16 7.1. a bsolute m aximum r atings ............................................................................................................................... .............................. 16 7.2. dc c haracteristics (vdd25=2.5v, vdd = 3.3v, vddio = 5v, t a = 25 )....................................................................................... 16 7.3. adc c haracteristics (avdd = 3.3v, t a = 25 ).............................................................................................................................. 17 7.4. dac c haracteristics (avdd = 3.3v, t a = 25 ).............................................................................................................................. 18 8. application circuits ....................................................................................................................... .................................................. 19 8.1. a pplication c ircuit 1 ( with c rystal ) .............................................................................................................................. ................ 19 8.2. a pplication c ircuit ( with r- oscillator ).............................................................................................................................. ........... 20 8.3. a pplication c ircuit 2 ( with r- oscillator ).............................................................................................................................. ........ 20 9. package/pad locations ...................................................................................................................... ............................................. 22 9.1. o rdering i nformation ............................................................................................................................... ...................................... 22 9.2. p ackage i nformation ............................................................................................................................... ........................................ 22 10. disclaimer..................................................................................................................... ........................................................................ 24 11. revision history ........................................................................................................................ ......................................................... 25
gpce001a ? generalplus technology inc. proprietary & confidential 3 oct 01, 2013 version: 1.7 16-bit sound controller with 256k x 16 flash memory 1. general description the gpce001a, a 16-bit architecture product, equips the newest 16-bit microprocessor, ?nsp? isa 1.3 developed by sunplus technology. this high processing speed ensures the ?nsp? isa 1.3 is capable of handling sophisticated digital signal processes (dsp) easily and rapidly. therefore, the gpce001a is especially targeted to the areas of dsp and speech/audio encode/decode. the wide range of cpu speed, from 0.1875mhz to 48mhz, makes the gpce001a easily to be applied in varieties of applications. the memory capacity contains 256k-word flash, and 2k-word working sram as well. other features include 32 programmable multi-f unctional i/os, three 16-bit timers/counters, 32768hz real time clock, low voltage reset/detection, eight channels of 12-bit adc (one channel built-in mic amplifier with auto gain controller), one 16-bit dac output and two pwm ios. a power saving mode, halt mode, is designed to only stop cpu clock. to save even more power, a sleep mode is featured to deactivate all of clocks. these two modes can be awakened from the interrupt source triggers. 2. application field ? intelligent interactive talking toys ? advanced educational toys ? general speech synthesizer ? long duration audio products 3. features ? 16-bit ?nsp? isa 1.3 microprocessor ? cpu clock: 0.1875mhz - 48mhz@6mhz crystal ? 256k-word flash memory and 256-word information block ? 2k-word cpu working sram ? chip operating voltage: 2.7v - 3.6v ? io operating voltage: 2.7v - 5.5v ? total of 32 programmable io including ioa(8) & iob(16) & ioc(8) ? crystal resonator & r-oscillator ? standby mode (clock stop mode) for power savings ? halt mode (only cpu clock stop) for power savings ? three 16-bit timers/counters ? one 16-bit dac output ? wakeup source from ioa key, timer/rtc ? 32768hz real time clock (rtc) ? eight channels of 12-bit ad converter ? adc external top reference voltage ? one generalplus serial interface i/o ? one spi serial interface i/o ? built-in microphone amplifier and agc function ? low voltage reset and low voltage detection ? watchdog enable ? ice function for development and download into flash memory
gpce001a ? generalplus technology inc. proprietary & confidential 4 oct 01, 2013 version: 1.7 4. block diagram
gpce001a ? generalplus technology inc. proprietary & confidential 5 oct 01, 2013 version: 1.7 5. signal descriptions mnemonic pin no. lqfp 128 pin no. type description port a, port b, port c ioa [15:8] 103,105 107-112 97,87,104-99 i/o ioa [15:8]: bi-directional i/o ports. it can be programmed to wakeup-able i/o pins. iob [15:0] 113 - 128 120-105 i/o iob [15:0]: bi-directional i/o ports. ioc [7:0] 65 - 72 72-65 i/o ioc [7 :0]: bi-directional i/o ports. nc 93 n/a - power & gnd vddio_1 73 73 p positive power supply for ioc vssio_1 74 74 g ground reference for ioc vddio_2 76 76 p positive power supply vssio_2 75 75 g ground reference vddio_3 129 121 p positive power supply for ioa , iob vssio_3 130 122 g ground reference for ioa , iob vddio_4, vddio_5 16 17 3 4 p positive power supply vssio_4, vssio_5 14 15 1 2 g ground reference vdd25_1 38 15 p positive power supply for core vss25_1 41 18 g ground reference for core vdd25_2 39 16 p positive power supply for oscillator and pll vss25_2 40 17 g ground reference for oscillator and pll nc 43 n/a - nc 42 n/a - avdd_1 56 47 p positive power supply for analog circuit including adc & mic avss_1 55 46 g ground reference for analog circuit including adc & mic avdd_2 52 43 p positive power suppl y for analog circuit including dac avss_2 54 45 g ground reference for analog circuit including dac vdd 36 13 p positive power for regulator and icesck, icesda, iceen, resetb, test, test2. vdd25o 37 14 p regulator output for connections to vdd25_1 and vdd25_2. clk system/ ice interface iceen 30 7 i ice (low)/free run (high) selection pin (floating as h) icesda 29 6 io ice serial data icesck 28 5 i ice clock xi 35 12 i oscillator crystal input xo / rosc 34 11 o oscillator crystal output/ rosc-input at rosc mode option (pin option in both rom-less and real chip) test 32 9 i test mode selection pin test2 33 10 i test mode for flash option (mask option in real chip) ri_xo 94 78 i rosc/crystal selection pin (no connect as crystal osc, tie vss as rosc) wdge 0(info) n/a i mask option (flash information block) (1: enable watch dog 0: disable)
gpce001a ? generalplus technology inc. proprietary & confidential 6 oct 01, 2013 version: 1.7 mnemonic pin no. lqfp 128 pin no. type description lvr_en 0(info) n/a i mask option (flash information block) (1: enable low voltage reset 0: disable) nc 47-49 n/a - dac dac1 50 41 o audio dac1 output dac_en 95 79 i dac enable signal with pull high. we strongly recommend connecting it with power(ex. vddio) adc micip 63 54 i mic amplifier input positive (internal floating) micin 62 53 i mic amplifier input negative (internal floating) mico 61 52 o mic amplifier output opi 60 51 i audio amplifier negative input agc 59 50 io agc by pass filter v_mic 58 49 o mic power output switch to avdd avref_top 57 48 i avref_top input avref_mid 64 55 o avref_top/2 output with buffer (adc maximum value voltage) avref_dac 53 44 o avref_da reference pin other signal resetb 31 8 i system reset pin low acti ve (internal 47kohms pull high resistor) vpp 104 n/a p flash vpp nc 1-13,18-27 n/a - nc 44-46,47-49 n/a - nc 77-92 n/a - nc 131-136 n/a - total: 136 pins for chip, 128 pins for lqfp 128 package.
gpce001a ? generalplus technology inc. proprietary & confidential 7 oct 01, 2013 version: 1.7 5.1. pad assignment this ic substrate should be connected to vss note1: to ensure the ic functions properly, please bond all vdd and vss pins. note2: the 0.1uf capacitor between vdd and vss should be placed to ic as close as possible.
gpce001a ? generalplus technology inc. proprietary & confidential 8 oct 01, 2013 version: 1.7 5.2. pin map
gpce001a ? generalplus technology inc. proprietary & confidential 9 oct 01, 2013 version: 1.7 6. functional description 6.1. cpu the gpce001a is equipped with a 16-bit ?nsp ? (read as ?micro-n-sp?) designed by sunplus. thirteen registers are available in ?nsp ? : r1 ~ r4 (general-purpose registers), sr1 ~ sr4 (secondary bank registers), pc (program counter), sp (stack pointer), base pointer (bp), sr (segment register) and fr (flag register). it provides inte rrupts, including fifteen fiqs (fast interrupt request) and sixteen irqs (interrupt request), plus one software-interrupt, break. moreover, a high performance hardware multiplier with the capability of fir filter calculation is also built-in to reduce the software multiplication loading. 6.2. memory 6.2.1. sram the amount of sram is 2k-word (including stack) ranged from $0000 through $07ff with two cpu-clock cycles access speed. 6.2.2. flash memory flash memory size is 256k words and its address is mapped from $04000 to $043fff. this flash memory is a high-speed memory, with 50ns access time, containing 256 words information block ranged from $2700 through $27ff as well as containing option information for gpce001a. the option in information block is described below. option_security: enable or disable ice read. option_wdog_en: enable or disable watchdog reset. option_para_wp: enable or disable flash write function in address range from $c000 through $ffff. option_main_wp: enable or dis able flash write function in address range from $10000 through $43fff. writing option into flash inform ation block is done by ide tool.
gpce001a ? generalplus technology inc. proprietary & confidential 10 oct 01, 2013 version: 1.7 6.3. pll, clock, power saving mode 6.3.1. pll (phase lock loop) the purpose of pll is to provide stable output frequency which takes the base frequency (from crystal) for reference. the pll frequency gain (output frequency/input frequency) ranges from 4 to 15. suppose base frequency is 6 mhz and pll frequency gain selects 8, the output frequency of pll is 48 mhz. 6.3.1.1. system clock basically, the system clock is provided by pll and determined by programming the p_systemclock (w). the default pll clock (pll) pumps to 6*f osc , that is 36mhz using 6mhz crystal and cpu clock is 4.5mhz (with default value: pll/8). 6.3.1.2. 32768hz rtc the real time clock (rtc) is normally used in watch, clock or other timing-based applications. a 2hz-rtc (0.5 seconds) function is available in gpce001a. the rtc counts the time as well as to wake cpu up whenever rtc occurs. time can be traced by the numbers of rtc occurrence. in addition, gpce001a supports 32768hz oscillator in strong mode and weak mode for power savings. in strong mode, 32768hz osc circuit in gpce001a always runs at the highest power consumption. on the other hand, 32768hz osc in gpce001a circuit run less power consumption in weak mode, but it must use a high-standard 32768hz external crystal such as seiko ssp_t6 or microcrystal cc5v-t1a. 6.4. power saving mode the gpce001a features a power savings mode (or called standby mode) for low power applications. to enter standby mode, the desired key wakeup port (ioa[15:8]) must be configured to input first. and read the p_ioa_data to latch the ioa state before entering the standby mode. also remember to enable the corresponding interrupt source(s) for wakeup. after that, stop the cpu clock by writing $5555 into p_systemsleep(w) to enter standby mode. in such mode, sram and i/os remain in the previous states until cpu being awakened. the wakeup sources in gpce001a include key wake up (ioa15 - 8), rtc wakeup, and irq1 - irq7. after gpce001a is awakened, cpu will continue to execute the program from the location it slept. programmer can also enable or disable the 32768hz rtc when cpu is in standby mode. 6.5. cpu halt mode the gpce001a features a cpu halt mode for power savings. in this mode, the cpu clock is turned off. 6.6. low voltage detection and low voltage reset 6.6.1. low voltage detection (lvd) the low voltage detect (lvd) reports the circumstance of present voltage. there are four lvd levels to be selected: 2.6v, 2.8v, 3.0v and 3.2v. those levels can be programmed via p_lvd_ctrl. as an example, suppose lvd is gi ven to 2.8v. when the voltage drops below 2.8v, the b12 of p_lvd_ctrl is read as high. in such state, program can be des igned to react this condition. 6.6.2. low voltage reset in addition to the lvd, the gpce001a provides another important feature, low voltage reset (lvr). with the lvr function, a reset signal is generated to reset system when the operating voltage drops below 2.4v for 4 consecutive pll system clock cycles. without lvr, the cpu becomes unstable and malfunctions when the operating voltage drops below 2.4v. using lvr, it will reset all functions to the initial operational (stable) states when the voltage drops below 2.4v. a lvr timing diagram is given as follows. 2.4v vdd pll tvdd tw tw=pll x 4 cycle lvr @ tvdd > tw treset reset treset = pll x 512 pll cycle 6.6.3. watchdog reset the gpce001a provides another important feature, watchdog reset. with the watchdog function, a reset signal is generated to reset system when watchdog counter is overflow and the option of option_wdog_en is enabled. the purpose of watchdog is to monitor whether the system operates normally. within a certain period, watchdog register must be cleared. if it is not cleared, cpu assumes the program has been running in an abnormal condi tion. as a result, the cpu will reset the system to the initial state and start running the program all over again.
gpce001a ? generalplus technology inc. proprietary & confidential 11 oct 01, 2013 version: 1.7 6.6.4. soft reset protection software reset. writes $5555 into p_system_reset will reset the whole system like hardware reset(pull low resetb pin), except a flag will set on in p_system_lvd_ctrl(r/w). 6.6.5. stack access protection gpce001a will be reset when stack operation (example push or pop) of cpu accesses the sram that is not in the defined range. the defined stack range uses stack top (p_stack_top) and bottom (p_stack_bottom) control register. 6.7. interrupt the gpce001a has 16 interrupt sources, grouped into two types, fiq (fast interrupt request) and irq (interrupt request). the priority of fiq is higher than irq. an irq can be interrupted by a fiq, but not by another irq. a fiq cannot be interrupted by any other interrupt sources. interrupt source interrupt name / fiq name irq priority timer a irq0_tma/fiq_tma 1(high) timer b irq1_tmb/fiq_tmb 2 timer c irq2_tmc/fiq_tmc 3 spi irq3_spi/fiq_spi 4 sio irq3_si/o 5 key wakeup irq5_key/fiq_key 6 ext1 irq5_ext1/fiq_ext1 7 ext2 irq5_ext2/fiq_ext2 8 4096hz irq6_4khz/fiq_4khz 9 2048hz irq6_2khz/fiq_2khz 10 512hz irq6_512hz/fiq_512hz 11 64hz irq7_64hz/fiq_64hz 12 16hz irq7_16hz_fiq_16hz 13 2hz irq7_2hz/fiq_2hz 14(low) 6.8. i/o three i/o ports are built in gpce001a - porta, portb, portc. the porta is an general purpose i/o with programmable wakeup capability, i.e. ioa[15:8] is the key wakeup port. user can latch data on p_ioa_data and enable the key wakeup function. wakeup is triggered when the porta state is different from latched data. furthermore, the i/o ports can be operated at 5v level, higher than the cpu core which is a 2.5v level system. suppose system operating voltage is running at 2.7v, vddio (power for i/o) operates from 2.7v to 5.5v. in such condition, the i/o pad is capable of operating from 0v to vddio. the following diagram is an i/o schematic. although data can be written into the same register through port_data and port_buffer, they can be read from different places, buffer(r) and data(r). register control logic pull high pull low pin pad buffer(r) data(r) port_data(w) port_buffer(w) port_dir(r/w) port_attr(r/w) in addition to a general purpose i/o port function, porta/b/c also shares/carries some special func tions. a summary of porta/b/c special functions is listed as follows: port special function function description ioa8 apwmo1 timera pwm output bpwmo1 timerb pwm output ioa9 irout ir output ioa10 feedback output2 work with ioa11 by adding a rc circuit between them to get an osc to ext2 interrupts. feedback input2 - ioa11 ext2 external interrupt source 2 (negative edge triggered) ioa12 feedback output1 work with ioa13 by adding a rc circuit between them to get an osc to ext1 interrupts. feedback input1 - ioa13 ext1 external interrupt source 1 (negative edge triggered)
gpce001a ? generalplus technology inc. proprietary & confidential 12 oct 01, 2013 version: 1.7 port special function function description ioa14 rtco real time clock output ioa15 rtci real time clock input iob6 apwmo2 timera pwm output iob7 bpwmo2 timerb pwm output iob10 sda serial interface data iob11 sck serial interface clock iob12 cs spi chip select iob13 ck spi clock iob14 di spi data input iob15 do spi data output ioc0 an0 adc channel 0 ioc1 an1 adc channel 1 ioc2 an2 adc channel 2 ioc3 an3 adc channel 3 ioc4 an4 adc channel 4 ioc5 an5 adc channel 5 ioc6 an6 adc channel 6 ioc7 an7 adc channel 7
gpce001a ? generalplus technology inc. proprietary & confidential 13 oct 01, 2013 version: 1.7 refer to the above table, the configuration of ioa10, ioa11, ioa12, ioa13 involves feedback function that an osc frequency can be obtained from ext1 (ext2) by simply adding a rc circuit between ioa10 (ioa12) and ioa11 (ioa13). 6.9. timer/counter gpce001a provides three 16-bit ti mers/counters - timera, timerb and timerc, or so called universal counters. the clock source of timer a/b/c are from clock source input1 and clock source input2 (as following table) which perform and operation to form varieties of combinations. when timer over flows, a timeout signal (taout) is sent to cpu interrupt module to generate a timer interrupt signal. in addition, timer a/b/c hardware interrupt events can be used to latch the dac audio output and trigger adc conversion. example to timer a, sending a write signal into tma_cnt, the value of tma_data (value=n) will reload into tma_cnt and set an appropriated clock source. timer will up-count from n, n+1, n+2? 0xffff. an int signal is generated at the moment of timer rolling over from ?0xffff? to ?0x0000?, and an int signal is processed by int controller immediately. at the same time, n will be reloaded into tma_cnt and start counting again. in timer a, the clock input 1 is a high frequency source and clock input 2 is a low frequency clock source. the combination of clock input 1 and 2 provides varieties of speeds to timera / countera - ?1? representing pass signal (not gating), and ?0? meaning timer deactivated. for instance, if input 1 =?1?, the clock is depending on input 2. if input 1 =?0?, the timera is deactivated. the ext1/ext2 is the external clock source. tmxsel input 1 input 2 0000 ?0? ?0? 0001 ?1? ?1? 0010 f rtc / ext1 ext2 0011 f pll ext2 0100 ext2 64hz 0101 ext2 16hz 0110 ext2 2hz 0111 ext2 ?1? 1000 f rtc / ext1 64hz 1001 f rtc / ext1 16hz 1010 f rtc / ext1 2hz 1011 f rtc / ext1 ?1? 1100 f pll 64hz 1101 f pll 16hz 1110 f pll 2hz 1111 f pll ?1? tapwmo tduty apwmo timera_timeout
gpce001a ? generalplus technology inc. proprietary & confidential 14 oct 01, 2013 version: 1.7 6.9.1. io pwm two io pwms which duty is selected from 1/16 to 14/16. example in the above figure is a 3/16-duration cycle. the apwmo waveform is made by selecting a pulse width through p_apwm_ctrl. as a result, each 16 cycles will generate a pulse width defined in control port. these pwm signals can be applied for controlling the speed of motor or other devices. 6.9.2. timebase timebase, generated by 32768hz crystal oscillator, is a combination of frequency selection. furthermore, timebase generates 4khz, 2khz, 512hz, 64hz, 16hz and 2hz interrupt sources (irq6, irq7) for real-time-clock. 6.10. sleep mode, wakeup, halt mode, and watchdog 6.10.1. sleep and wakeup modes 1) sleep: after power-on reset, ic starts running until a sleep command is issued. when a sleep command is accepted, ic will turn the system clock (pll) off. after all, it enters sleep mode. 2) wakeup: cpu awaking from sleep mode requires a wakeup signal to turn the system clock (pll) on. the fiq/irq signal makes cpu complete the wakeup process and initialization. the cpu wakeup source is given in the following table. 3) halt mode: halt mode is for power saving. in this mode, cpu clock is turned off. wakeup source fiq source timer a interrupt timer b interrupt timer c interrupt spi interrupt ext1/ext2/key rtc 6.11. adc (analog to digital converter) / dac the gpce001a has eight channels of 12-bit a/d (analog to digital converter). the function of an a/ d converter is to convert analog quality signal, e.g. a voltage into a digital word or input source, can be eight channels line-in from ioc[7:0] or one channel microphone input through amplifier and agc controller. the mic amplifier circuit is capable of reducing common mode noise by transmitting signals through mic fully differential input. moreover, an external resistor can be applied to adj ust microphone gain and time of agc operating. the adc needs to select source of line-in before converting. 6.12. 16-bit dac audio driver the gpce001a provide one 16-bit dac for audio output. 6.13. serial interface i/o (sio) serial interface i/o offers a one-bit serial interface that communicates with other devices. th is serial interface is capable of transmitting or receiving data vi a two i/o pins, iob11 (sck) and iob10 (sda). sck sda ax ax-1 a0 dx dx-1 d0 dx dx-1 d0 start sio write mode : read/write bit waveform = 0 stop sio read mode : ax ax-1 a0 dx dx-1 d0 dx dx-1 d0 start sck sda read/write bit waveform = 1 stop
gpce001a ? generalplus technology inc. proprietary & confidential 15 oct 01, 2013 version: 1.7 6.14. spi a serial peripheral interface (spi ) controller is built in gpce001a to facilitate communicating with other devices and components. there are four control signals on spi - spics (iob12), spick (iob13), sdi (iob14), and sdo (iob15). d7 d6 d4 d5 d2 d3 d0 d1 d7 d6 d5 d3 d4 d2 d0 d1 spick(pol=0) spick(pol=1) sdo sdi spics 6.15. audio algorithm the following speech types can be used in gpce001a: pcm, log pcm, sacm_s200 sacm_s480, sacm_s530, sacm_s720, sacm_a1600, sacm_a1601, sacm_a3200, sacm_a3600, sacm_dvr1600 (digital voice recorder), and sacm_dvr4800. for melody synthesis, the gpce001a provides a sacm_ms01 (fm synthesizer) and sacm_ms02 wave-table synthesizer. 6.16. security function security function is able to pr otect code been read or written. when program is downloaded into flash memory, program can be read/write protected by ide tools for security purpose. by writing security enable option, the ide fu nction will be disabled except the flash mass erase function in ice mode. after mass erase the flash, the security option will be enabled again, to enable the security option cannot limit cpu to read flash content in free run mode.
gpce001a ? generalplus technology inc. proprietary & confidential 16 oct 01, 2013 version: 1.7 7. electrical specifications 7.1. absolute maximum ratings characteristics symbol min. max. unit regulator supply voltage vdd -0.3 4.0 v io pad supply voltage vddio -0.3 6.0 v analog supply voltage avdd -0.3 4.0 v core supply voltage vdd25 -0.3 3.0 v input voltage range v in -0.3 vddio + 0.5 v esd protection(hbm) v esd 2k - v operating temperature range t a 0 +60 storage temperature range t sto -50 +150 note: stresses beyond those given in the absolute maximum rating ta ble may cause operational errors or damage to the device. for no rmal operational conditions see dc electrical characteristics. 7.2. dc characteristics (vdd25=2. 5v, vdd = 3.3v, vddio = 5v, t a = 25 ) limit characteristics symbol min. typ. max. unit test condition operating voltage (io) vddio 2.7 5.0 5.5 v io vdd operating voltage (regulator) vdd 2.7 3.3 3.6 v 3.3v for regulator power operating voltage (analog) avdd 2.7 3.3 3.6 v 3.3v for analog power operating voltage (core) vdd25 2.4 2.5 2.7 v 2.5v for core power regulator max output current i(vdd25o) - - 60 ma vdd = 3.0v, vdd25o= 2.5v, (regulator output) operating current i op - 40 - ma pll = 48mhz, ad, dac disable, no loading ; vdd25 = 2.5v; vdd =3.3v; vddio = 5.5v standby current i stb - 10 30 a disable 32khz crystal input high level v ih 0.7 vddio - - v - input low level v il - - 0.3 vddio v - io output high current i oh - -6.0 - ma v oh = 0.9 vddio io output low current i ol - 12.0 - ma v ol = 0.1 vddio input pull-low resistor (ioa [8:13], iob) r pl1 - 90 - k v in = vddio input pull-low resistor (ioa [14,15], ioc) r pl2 - 410 - k v in = vddio input pull-high resistor (ioa, iob, ioc) r ph - 130 - k v in = vss
gpce001a ? generalplus technology inc. proprietary & confidential 17 oct 01, 2013 version: 1.7 7.2.1. r-osc frequency vs resistor 7.2.1.1. vdd25=2.5v, vdd = 3.3v, vddio = 5v, t a = 25 rosc freq vs. resistor 0 2 4 6 8 10 12 0 25 50 75 100 125 150 175 rosc(kohm) freq(mhz) 7.2.1.2. operation curren t (vdd25=2.5v, vdd = 3.3v, vddio = 5v, t a = 25 ) operating current(ad,adc off,vdd=3.3v) 0 10 20 30 40 0204060 pll(mhz) iop(ma) crytal=6m operating current(ad,adc off,vdd=3.3v) 0 10 20 30 40 0 204060 pll(mhz) iop(ma) rosc=47k 7.3. adc characteristics (avdd = 3.3v, t a = 25 ) limit characteristics symbol min. typ. max. unit adc line_in input voltage range from ioc[7:0] vinl (note 1) avss-0.3 - avdd+0.3 v adc microphone input voltage range vinm avss-0.3 - avdd+0.3 v external adc top voltage vextref (note 2) 2.0 - avdd+0.3 v resolution of adc reso - - 12 bits signal-to-noise plus distortion of adc fr om line in sinad (note 4) - 60 - db effective number of bit enob (note 5) - 9.6 - bits integral non-linearity of adc inl - 3.0 - lsb (note 3) differential non-linearity of adc dnl (note 6) - 1.0 - lsb no missing code - 12 - bits max adc clock - - 3.375 mhz ad conversion rate f conv - - 150k hz note1: internal protection diodes clamp the analog input to avdd and avss. these diodes allow the analog input to swing from (avss-0 .3v) to (avdd+0.3v) without causing damage to the devices. note2: the adc performance is limited by the sy stem?s noise level, so the gpce001a just guarantee with the 8-bit accuracy when avref_ top is 2v. note3: lsb means least significant bit. with vinl=3v, 1lsb=3v/2^12= 0.732 mv. note4: the sinad testing condi tion at vinlp-p=3.1v, f conv = 48khz, fin=0.997khz sine waves at avdd=3.3v from the ioc [7:0] input. note5: enob=(sinad-1.76)/6.02. note6: the adc of gpce001a can guarantee no missing code.
gpce001a ? generalplus technology inc. proprietary & confidential 18 oct 01, 2013 version: 1.7 7.4. dac characteristics (avdd = 3.3v, t a = 25 ) limit characteristics symbol min. typ. max. unit resolution of dac reso - 16 - bit signal to noise ratio of dac snr - 90 - db dynamic range dr - 85 - db sample rate f s - 200k - hz thd+n at fs f out =0.997khz - -60 - db output loading rl 125 - - chm output range input=full scale - 60% - avdd note1: the thd+n testing condition at avdd=3.3, f s =48khz, fin=0.997khz input at rl=125 ohm 7.4.1. pull high resister and vddio rph t est 0 50 100 150 200 250 300 350 23 456 vddio(v ) rph(kohm) 7.4.2. pull low resister and vddio rpl test 0 250 500 23456 vddio(v) rpl (kohm) pa[14,15];pc[7:0 ] other i/o rt po rt 7.4.3. i/o output high current i oh and v oh 7.4.4. i/o output low current i ol and v ol iol test(@vol=1v) -25 -20 -15 -10 -5 0 2 3 4 5 6 vddio(v) pb[13,14] other i/o port iol(ma) ioh test 0 2 4 6 8 23 456 vdd(v) other i/o port pb[13,14] -20
gpce001a ? generalplus technology inc. proprietary & confidential 19 oct 01, 2013 version: 1.7 8. application circuits 8.1. application circuit 1 (with crystal) gpce001a mic 3k 3k 1k 0.22 220 0.22 5.1k 0.22 0.1 0.1 reset vdd5 0.1 1k 10 k 0.22 6 0.1 100 4 5 3 2 1 87 ioa[15:8] iob[15:0] avdd 100 0.1 vdd 0.1 gpce001a application circuit audio amplifier, for 3-battery use only) 0.1 47 speaker1 4.7 470k xi xo 12-20 p* 6mhz ioc[7:0] 100 0.1 gpy0029b vdd 5 2 1 3 avdd 100 0.1 100 0.1 100 0.1 100 0.1 100 0.1 vdd 100 0.1 gpy0030a 0.1 0.1 100 100 5000p avdd (3.3v) vdd25 vdd33 33 vdd 33 vdd 33 vdd 33 vdd 33 res b et dac1 vdd25_2 vss25_2 vdd25_1 vss25_1 vdd25o avdd_1 avss_1 avdd_2 avss_2 vdd vss25_1 ioc[7:0] iob[15:0] ioa[15:8] io vss _1 io vdd _1 io vss _2 io vdd _2 io vss _3 io vdd _3 io vss _4 io vdd _4 io vss _5 io vdd _5 avref_dac avref_top agc opi mico micn micp vmic 12-20 p* dac_en vdd 33 note*: these capacitor values are for design guidance only. different capacitor values may be required for different crystal/resonato r used.
gpce001a ? generalplus technology inc. proprietary & confidential 20 oct 01, 2013 version: 1.7 8.2. application circuit (with r-oscillator) gpce001a mic 3k 3k 1k 0.22 220 0.22 5.1k 0.22 avref_top 0.1 0.1 reset res b vdd dac1 0.1 1k 10k 0.22 6 0.1 100 4 5 3 2 1 87 ioa[15:8] iob[15:0] avdd 100 0.1 avdd_2 avss _2 vdd 0.1 vdd vss25_1 gpce001a application circuit audio amplifier, for 2-battery use only) 0.1 47 speaker1 4.7 470k xo ioc[7:0] 100 avref_dac 0.1 avdd 100 0.1 avss_1 avdd _1 100 0.1 100 0.1 100 0.1 100 0.1 vdd 100 0.1 vdd25 51k ioa[15:8] iob[15:0] ioc[7:0] io vdd _2 io vss _2 io vdd _1 io vss _1 io vdd _3 io vss _3 io vdd _4 io vss _4 io vdd _5 io vss _5 vmic micp micn mico opi agc ri_xo gpy0030a vss25 _1 vdd25o vdd25_2 vss25_2 vdd25 _1 0.1 0.1 100 100 5000p avdd (3.3v) 33 et vdd 25 33 vdd 33 vdd 33 vdd 33 vdd 33 dac_en vdd 33
gpce001a ? generalplus technology inc. proprietary & confidential 21 oct 01, 2013 version: 1.7 application circuit 2 (with r-oscillator) gpce001a mi c 3k 3k 1k 0.22 220 0.22 5.1k 0.22 avref_top 0.1 0.1 reset res b vdd5 dac1 0.1 1k 10 k 0.22 6 0.1 100 4 5 3 2 1 87 ioa[15:8] iob[15:0] vdd5(5v) avdd 100 0.1 avdd _2 avss_2 vdd 0.1 vdd vss25_1 gpce001a application circuit audio amplifier, for 3-battery use only) 0.1 47 speaker1 4.7 470k xo ioc[7:0] 100 avref_dac 0.1 gpy0029b vdd 5 2 1 3 avdd 100 0.1 avss_1 avdd_1 100 0.1 vdd5(5v) 100 0.1 vdd5(5v) 100 0.1 vdd5(5v) 100 0.1 vdd5(5v) 100 0.1 vdd2 5 51k ioa[15:8] iob[15:0] ioc[7:0] io vdd _2 io vss _2 io vdd _1 io vss _1 io vdd _3 io vss _3 io vdd _4 io vss _4 io vdd _5 io vss _5 vmic micp micn mico opi agc ri_xo gpy0030a vss25_1 vdd25o vdd25_2 vss25_2 vdd25 _1 0.1 0.1 100 100 5000p avdd (3.3v) et vdd2 5 vd d33 dac_en vdd5(5v)
gpce001a ? generalplus technology inc. proprietary & confidential 22 oct 01, 2013 version: 1.7 9. package/pad locations 9.1. ordering information product number package type GPCE001A-NNNV-C chip form gpce001a-nnnv-ql09x halogen free package note1: code number is assigned for customer. note2: code number (n = a - z or 0 - 9, nn = 00 - 99); version (v = a - z). note3: package form number (x = 0 - 9, serial number). 9.2. package information 9.2.1. lqfp 128 outline dimensions dimension in inch symbol min. typ. max. a - - 1.60 a1 0.05 - 0.15 a2 1.35 1.40 1.45 b 0.13 0.16 0.23 c 0.09 - 0.20 d 16.00 bsc. d1 14.00 bsc. e 16.00 bsc.
gpce001a ? generalplus technology inc. proprietary & confidential 23 oct 01, 2013 version: 1.7 dimension in inch symbol min. typ. max. e1 14.00 bsc. e 0.40 bsc. l 0.45 0.60 0.75 l1 1.00 ref 0 3.5 7
gpce001a ? generalplus technology inc. proprietary & confidential 24 oct 01, 2013 version: 1.7 10. disclaimer the information appearing in this public ation is believed to be accurate. integrated circuits sold by generalplus technology are covered by the warranty and pa tent indemnification pr ovisions stipulated in the terms of sale only. generalplus makes no warranty, express, statutory implied or by description regarding the information in this pu blication or regarding the freedom of the described chip(s) from patent infringement. furthermore, generalplus makes no warranty of merchantability or fitness for any purpose. generalp lus reserves the right to halt production or alter the specifications and prices at any time wi thout notice. accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. produc ts described herein are intended for use in normal commercial app lications. applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equip ment, are specifically not recommended without additional processing by generalplus for such app lications. please note that application circuits illustrated in this document are for reference purposes only.
gpce001a ? generalplus technology inc. proprietary & confidential 25 oct 01, 2013 version: 1.7 11. revision history date revision # description page oct. 01, 2013 1.7 add comair logo to the cover page may 09, 2011 1.6 rename one nc pin to dac_ en and modify related application circuit. 5,6,7,8, 19,20,21 sep. 15, 2009 1.5 modify 7.2 dc characteristics. 16 jan. 12, 2009 1.4 1. modify ?signal descriptions? in section 5. 2. modify ?application ci rcuit2? in section 8.3. 5 21 sep. 09, 2008 1.3 modify section 8. application circuits. 19-21 jul. 04, 2007 1.2 1. modify the ?signal descriptions? in section 5. 2. modify the ?pad assignment? in section 9.1. 3. add the ?package information? in section 9.3. 5 21 22 jan. 05, 2007 1.1 rename to match the real body function. 1 oct. 05, 2006 1.0 original 22

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